Mehdi Bouama8-bit Multicycle Processor
RTL verification and DE1 port preparation for a multicycle 8-bit processor, extending an existing university RTL design.
- VHDL
- Quartus
Verification
Verification details available in the case study.
Mehdi Bouama
M2 SETI student specializing in Architecture -- Embedded Systems, FPGA and Digital Design
Work
Technical Focus
FPGA / RTL
VHDL digital design and RTL development, from datapath and control-FSM architecture to FPGA integration.
Digital Architecture
Processor and datapath architecture: control FSMs, ALU design and instruction timing.
Rigorous Verification
Exhaustive GHDL testbenches with independent reference models and continuous integration.
Embedded Systems / SoC
Embedded C/C++, Linux/Raspberry Pi integration and sensor/actuator interfacing.
Hardware-Software Co-design
Autonomous robotics combining reactive software control with sensor and actuator hardware.
Featured Work
View case study
16-bit Integer Square Root Core
A synthesizable unsigned 16-bit integer square-root core, exhaustively verified across all 65,536 inputs and prepared for a Terasic DE1 port.
- VHDL
- Quartus
Verification
Verification details available in the case study.
CoVAPSy Autonomous Vehicle
Navigation and control software for a 1/10-scale autonomous race vehicle, built for the collaborative ENS Paris-Saclay CoVAPSy 2026 competition.
- Python
- Raspberry Pi
Verification
Verification details available in the case study.
Sequential Search & Multiplier
Two small sequential VHDL cores -- a searchx sequential-search engine and an 8x8 iterative shift-add multiplier -- each exhaustively or near-exhaustively verified and packaged for a Terasic DE1.
- VHDL
- Quartus
Verification
Verification details available in the case study.
Technical Profile
FPGA / RTL Design
VHDL, FSMs, datapath design, processor architecture and digital arithmetic; Quartus, and Vivado for a mini-project.
Verification
VHDL testbenches, exhaustive verification, independent reference-model checking and GitHub Actions CI.
Embedded Systems & Software
C, C++, Python, Linux/Raspberry Pi, ESP32, STM32 (academic project), I2C, UART, PWM.
Tools
Git, CMake, Make.
Additional Projects
IAQ ESP32-S3 -- Indoor Air Quality Monitoring
Additional project
Contribution to a collaborative indoor-air-quality monitoring project through development of the web platform/dashboard and associated application/software integration. System context: an ESP32-S3 firmware reads CO2, TVOC, CO, temperature and humidity sensors and reports over HTTPS to a Flask backend and a real-time web dashboard.
- ESP32
- Python
Background
Education
Master 2 SETI
Université Paris-Saclay — 2026-09 –
Embedded Systems and Information Processing -- Specialization: Architecture.
Master 1 E3A
Université Paris-Saclay — 2025-09 – 2026-06
Autonomous Systems, Embedded Intelligence and Information Processing.
Bachelor Year 3 (L3) E3A
Université Paris-Saclay — 2024-09 – 2025-06
Electronics, Electrical Energy and Automation Engineering.
Bachelor's Degree - Electronics
USTHB, Algiers — 2021-09 – 2024-06
Foundational electronics degree.
Professional Experience
Private Tutor - Self-Employed
Self-employed — 2024-09 –
Mathematics, physics, electronics and programming; individualized tutoring from secondary school to post-secondary level, with exercises adapted to each student's needs.
Electrical Engineering Job-Shadowing Internship
EPTV, Algiers — 2023-06 – 2023-06
Two-week observation placement.
About
I am a final-year Master's student in Embedded Systems and Information Processing (M2 SETI, Architecture specialization) at Université Paris-Saclay. I am particularly interested in digital hardware design, system architecture, and work at the intersection of RTL design, verification and hardware/software integration.
I am primarily looking for a 6-month final-year internship, available from 18 March 2027; my programme also allows internships of 4 to 6 months. My main targets are FPGA and RTL design, digital and IP design, SoC design/integration, processor and microarchitecture work, hardware/software co-design and hardware acceleration, ideally combining design with verification. I currently work with VHDL and would also like to deepen my experience with Verilog/SystemVerilog in this type of role.
I am also open to hardware-adjacent roles in RTL/SoC verification, ASIC front-end, high-level synthesis (HLS), FPGA/SoC validation, embedded Linux — BSP and drivers — or low-level firmware.
Contact
mehdi.bouama.pro@gmail.com