16-bit Integer Square Root Core

Case Study

16-bit Integer Square Root Core. A small, synthesizable VHDL core computing floor(sqrt(X)) for a 16-bit unsigned input, exhaustively verified against every possible input and prepared for a Terasic DE1 port.

Context & Challenge

The goal was a compact, self-contained digital-design and FPGA portfolio project: a synthesizable unsigned 16-bit integer square-root core with a genuinely exhaustive verification story, not a spot-checked one, and a clean FPGA integration around it.

Scope & Responsibilities

The core, its testbenches and the DE1 integration are Mehdi Bouama’s work. The core computes floor(sqrt(X)) as an 8-bit result from a 16-bit unsigned input using an iterative binary digit-by-digit, restoring shift-and-subtract architecture: each of 8 compute iterations forms a trial value for the next root bit and tests a candidate subtraction, keeping the updated remainder if it is accepted and the previous remainder otherwise, from the most significant root bit to the least significant.

Architecture / System Design

The interface is a simple accept-then-pulse protocol: X_in is captured when start is accepted in the idle state, later changes to X_in do not affect the active calculation, and done pulses for one clock period when the result is valid. A start asserted during computation is ignored; if held high, it is accepted again once the core returns to idle. On the DE1 wrapper, a rising transition on SW9 is converted into a one-shot pulse to avoid repeated board-level launches.

Implementation

Board control on the Terasic DE1 (Cyclone II EP2C20F484C7, 50 MHz CLOCK_50) uses SW7:0 for the byte value, SW8 to select the low or high input byte, SW9 as launch control, KEY0 as active-low reset, a latched LEDR0 completion indicator (latched because done lasts only one clock period, with no full mechanical debounce on SW9), and HEX2-HEX0 for the decimal result.

Verification & Evidence

The permanent GHDL test suite covers directed boundary and representative arithmetic cases, exact result and completion latency, asynchronous reset (including reset during computation), input capture at an accepted start, ignored starts during computation, held-high start behavior, successive transactions, protection against meta-values, and, exhaustively, 65536 vectors possible 16-bit inputs against an independent integer binary-search reference model, deliberately structured differently from the core’s own restoring recurrence. The result: true.

Latency is architectural, not a physical measurement: from an accepted start, the result and done are asserted after 9 clock periods, which at the DE1’s nominal 50 MHz corresponds to 180 ns – this is a simulation-confirmed clock-period count, not a timing-closed physical result.

DE1 integration is prepared and statically reviewed: true.

The historical university coursework version of this core is documented separately from that current-wrapper status. sqrt16.vhd ran on a physical DE1 in the coursework: the historical Quartus project completed Analysis & Synthesis and the Fitter, TimeQuest was run, and programming files exist. The coursework report records the board observations 9 -> 3, 25 -> 5 and 256 -> 16, together with the done LED behavior. The historical core is byte-identical to the core pinned by this case study, but the historical wrapper is not the current public wrapper, so hardware validation of the current wrapper is not established. TimeQuest was run historically; no timing closure, 50 MHz closure or validated Fmax is claimed.

Results

The exhaustive sweep of every possible 16-bit input completes with zero mismatches, and the fixed 9-clock-period latency is confirmed by the testbench’s protocol checks. No Fmax, timing-closure result or other physical-implementation metric is claimed; at the time that the source revision referenced by this case study was reviewed, its GitHub Actions workflow had not yet executed, and no CI result is attributed to that referenced revision.

Limitations

This is a deliberately compact implementation: no pipelining, no floating-point square root, no signed inputs, no parameterized operand width, no AXI or Wishbone interface, and no full mechanical switch debounce circuit on the DE1 wrapper. For the current public wrapper, Quartus Analysis & Synthesis, Fitter, Assembler and TimeQuest results and testing on physical DE1 hardware are not established; the historical coursework DE1 execution described above does not extend to it, and no timing closure is claimed.

Key Takeaways

An exhaustive 65,536-input sweep is small enough to be genuinely exhaustive rather than merely large, and building the reference model as an independent binary search – not a mirror of the DUT’s own restoring recurrence – is what makes that sweep meaningful rather than a self-fulfilling check. The same discipline carried through to the DE1 side: stating plainly what GHDL-level synthesis checks do and do not establish, rather than letting a passing local build imply more than it does.

Artifacts / References

Public repository: github.com/mahdidou711/vhdl-integer-sqrt.