Mehdi Bouama8-bit Multicycle Processor
RTL verification and DE1 port preparation for a multicycle 8-bit processor, extending an existing university RTL design.
- VHDL
- Quartus
Verification
Verification details available in the case study.
Projects
Featured Work
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16-bit Integer Square Root Core
A synthesizable unsigned 16-bit integer square-root core, exhaustively verified across all 65,536 inputs and prepared for a Terasic DE1 port.
- VHDL
- Quartus
Verification
Verification details available in the case study.
CoVAPSy Autonomous Vehicle
Navigation and control software for a 1/10-scale autonomous race vehicle, built for the collaborative ENS Paris-Saclay CoVAPSy 2026 competition.
- Python
- Raspberry Pi
Verification
Verification details available in the case study.
Sequential Search & Multiplier
Two small sequential VHDL cores -- a searchx sequential-search engine and an 8x8 iterative shift-add multiplier -- each exhaustively or near-exhaustively verified and packaged for a Terasic DE1.
- VHDL
- Quartus
Verification
Verification details available in the case study.
Additional Projects
IAQ ESP32-S3 -- Indoor Air Quality Monitoring
Additional project
Contribution to a collaborative indoor-air-quality monitoring project through development of the web platform/dashboard and associated application/software integration. System context: an ESP32-S3 firmware reads CO2, TVOC, CO, temperature and humidity sensors and reports over HTTPS to a Flask backend and a real-time web dashboard.
- ESP32
- Python